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F75125 serial vid, parallel vid translator for amd am2 and am2+ release date: mar, 2008 version: 0.16p
finte k feature integration technology inc. v0.16p 1 F75125 F75125 datasheet revision history version date page revision history 0.10p jun, 2007 preliminary version 0.11p jul, 2007 17 22 add register description company address 0.12p jul, 2007 8 add electrical characteristics 0.13p sep, 2007 1 16 19 correct over voltage max a\value:2.325v add vsi/vso illustration revise register description 0.14p oct, 2007 27 remove ?g? from ordering information 0.15p feb, 2008 4 5 6 7 8 17 25 26 27 32 add svi output and psi description in general description add svi output in features add psi in features revise pin configuration add svi output related pin descriptions in nb related pins set vid_out[2] and vid_out[3] to multi-function pins with svc_out and svd_out add nb off code and power saving mode description add vdd and vdd_nb follow mode register add vdd0,1 and vdd_nb svid value monitor function register add vdd timeout set register add serial vid output application circuit 0.16p mar, 2008 25 26 27 27 28 register 0x08 renamed to vsi/vso 1 register 0x09 renamed to vsi/vso 2 add register 0x10 description add register 0x11 description add register 0x12 description
finte k feature integration technology inc. v0.16p 2 F75125 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support applia nces, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for any damages resulting from such improper use or sales.
finte k feature integration technology inc. v0.16p 3 F75125 table of contents 1 general description ............................................................................................................ ............................................ 5 2 feature ........................................................................................................................ ............................................................. 5 3 pin configuration .............................................................................................................. ................................................ 7 4 pin description................................................................................................................ ..................................................... 8 4.1. p ower p in ............................................................................................................................... ............................................ 8 4.2. n orth b ridge v oltage p in / v oltage r egulator s et t rap p in ................................................................................... 8 4.3. vid p in ............................................................................................................................... ................................................. 9 4.4. p ower g ood p in ............................................................................................................................... .................................. 9 4.5. v oltage s ense i nput /v oltage s ense o utput p in ........................................................................................................ 10 4.6. i2c i nterface p in ............................................................................................................................... .............................. 10 4.7. m iscellaneous p in ............................................................................................................................... ........................... 10 5 electrical char acteristic...................................................................................................... ..................................11 5.1 a bsolute m aximum r at i n g s ............................................................................................................................... ........... 11 5.2 dc c haracteristics ............................................................................................................................... ......................... 11 6 functional description ......................................................................................................... ...................................... 14 6.1 l inear c on p arallel vid i nterface ............................................................................................................................ 14 6.2 s erial vid i nterface ............................................................................................................................... ....................... 16 6.3 2-b it b oot c ode and vfixen m ode ............................................................................................................................. 18 6.4 n orth b ridge r eference v oltage and e nable .......................................................................................................... 18 6.5 p ower s av i n g m ode ............................................................................................................................... ......................... 19 6.6 core_type...................................................................................................................... ............................................... 20 6.7 v oltage s ense i nput / v oltage s ense o utput ............................................................................................................. 20 6.8 i2c i nterface ............................................................................................................................... .................................... 21 7 register description (i2c address = 0x5c)...................................................................................... .................... 22 7.1 vddnb voltage value r egister ? i ndex 00 h ............................................................................................................ 22 7.2 vdd0 voltage value r egister ? i ndex 01 h ............................................................................................................... 23 7.3 vdd1 voltage value r egister ? i ndex 02 h ............................................................................................................... 23 7.4 vid k ey protect r egister ? i ndex 03 h ..................................................................................................................... 24 7.5 vddnb voltage offset value r egister ? i ndex 04 h ................................................................................................ 24 7.6 vdd0 voltage offset value r egister ? i ndex 05 h ................................................................................................... 24 7.7 vdd1 voltage offset value r egister ? i ndex 06 h ................................................................................................... 25
finte k feature integration technology inc. v0.16p 4 F75125 7.8 vddnb step time r egister ? i ndex 07 h ................................................................................................................ 25 7.9 vsi/vso 1 o ver v oltage select r eading r egister ? i ndex 08 h ............................................................................ 25 7.10 vsi/vso 2 o ver v oltage select r eading r egister ? i ndex 09 h ............................................................................ 26 7.11 vdd0, vdd1 and vddnb manual enable r egister ? i ndex 0a h .......................................................................... 26 7.12 nb_vref v oltage r eading r egister (lsb) ? i ndex 0b h ...................................................................................... 26 7.13 vddnb svi o utput r eading r egister (lsb) ? i ndex 0c h .................................................................................... 27 7.14 vdd0 svi o utput r eading r egister (lsb) ? i ndex 0d h ........................................................................................ 27 7.15 vdd1 svi o utput r eading r egister (lsb) ? i ndex 0e h ........................................................................................ 27 7.16 slotocc c ontrol e nable r eading r egister ? i ndex 0f h ................................................................................... 27 7.17 vdd_nb v oltage v alue r egister ? i ndex 10 h ....................................................................................................... 27 7.18 vdd0 v oltage v alue r egister ? i ndex 11 h ............................................................................................................. 27 7.19 vdd1 v oltage v alue r egister ? i ndex 12 h ............................................................................................................. 28 7.20 vid t imeout v alue s elect r egister ? i ndex 13 h .................................................................................................... 28 7.21 chip id1 r egister ? i ndex 5a h ............................................................................................................................... .... 28 7.22 chip id2 r egister ? i ndex 5b h ............................................................................................................................... ..... 28 7.23 v ersion id r egister ? i ndex 5c h ............................................................................................................................... .28 7.24 v endor id1 r egister ? i ndex 5d h ............................................................................................................................... 28 7.25 v endor id2 r egister ? i ndex 5e h ............................................................................................................................... 28 8 ordering information ........................................................................................................... ....................................... 29 9 package dimensions (28-ssop) ................................................................................................... .................................. 29 10 application circuit ............................................................................................................ ............................................ 32
finte k feature integration technology inc. v0.16p 5 F75125 1 general description the serial vid interface (svi)/ parallel vid interface (pvi) translator,F75125, which can translate pvi to pvi and svi to pvi for amd am2 or am2+ platform and output a programmable reference voltage of north bridge voltage (v nb ) to an external single phase pwm by decoding serial vid. or, it can translate svi to svi and pvi to svi for amd am2 or am2+ platform. in the pvi output application, the F75125 can replace the hybrid (pvi+ svi) or svi voltage regulator by the original pvi voltage regulator controller to save th e extra cost. the F75125 supports vddio, vdda, and cpu power good input, cpu_pg_in, such as from the s outh bridge, sb600, to control the signal, vr_en to enable the vr controller. f 75125 supports all am2+ new features including core_type and vfixen. the core_type is used to indicate am2 or am2+ plac ed, and the vfixen paired with svc and svd let voltage regulator output a fixed voltage. in this application of the F75125, vid[5] is recommended to pull low ,so the vid output [4:0] is corresponding to output from 0.775 to 1.550v. in concern of mapping svi to pvi, vid table on-the-fly tuning is constrained in 0.800v to 1.550v. the voltage sense input (vsi)/voltage sense output (vso) also provide the similar functi on, but the tuning range up to 2.325v. in the svi output application, the F75125 will issue svi off code to vdd_nb to avoid vdd_nb mis-action when am2 is implemented. in svi output mode, t he F75125 also supports psi (bit7 of svi command). the F75125 is ssop-28 package and powered by 3.3vsb. 2 feature ? serial vid input to parallel vid output or parallel vi d input to parallel vid output translation for parallel vid interface voltage regulator controller ? serial vid input to serial vid output or parallel vid input to serial vid output translation for hybrid/serial vid interface voltage regulator controller ? serial or parallel vid mapping table is adjustable to tune voltage regulator controller output. ? programmable reference voltage output for north bridge voltage for over or under voltage in pvi output mode ? vfixen, svc, scd translation to pvi voltage regulator realizes am2+ fixed voltage output to cpu function ? support core_type input to indicate am d processor family 0fh,am2 or 10h,am2+ ? support vddio, vdda, cpu power good, cpu_pg_in, input to generate voltage regulator controller enable signal, vr_en, and cpu power good output, cpu_pg_out, to cpu and voltage regulator.
finte k feature integration technology inc. v0.16p 6 F75125 ? 2 sets of voltage sense input (vsi) and voltage sense output (vso) for over voltage vcore and v nb beyond maximum of vid table, 1.55v. ? i2c interface is built-in to fine tune vcore and v nb output. ? power saving mode supported in both am2+ platform ? powered by 3.3vsb and ssop-28 package
finte k feature integration technology inc. v0.16p 7 F75125 3 pin configuration figure1. F75125 pin configuration
finte k feature integration technology inc. v0.16p 8 F75125 4 pin description 4.1. power pin pin no. pin name type description 4 vsb3v p 3.3v stand by power 6 vdda p vdda input 8 vddio p vddio power 26 vss p ground 4.2. north bridge voltage pin/ voltage regulator set trap pin pin no. pin name type pwr description 3 vref_nb aout vsb3v in pvi output mode, reference voltage output to external single phase pwm to supply v nb . 5 nb_en#/vr_trap o 12 vsb3v pull high to 3,3vsb before po k, the F75125 will enter svi output mode, or the F75125 is set to pvi output mode. in pvi output mode, nb_en# is an external single phase pwm enable signal. p - power pins in st - ttl level input pin with schmitt trigger in lv - low level input, transient point at 0.9v i/od 12st5v - ttl level bi-directional pin with schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance i/od 12st - ttl level bi-directional pin with schmitt trigger, open-drain output with 12 ma sink capability. i/od 12lv - low level input, transient point at 0.9v , open-drain output with 12 ma sink capability o 12 - output pin with 12ma sink/driving capability. od 12 - open-drain output pin with 12ma sink capability. ain - input pin (analog). aout - output pin (analog).
finte k feature integration technology inc. v0.16p 9 F75125 4.3. vid pin pin no. pin name type pwr description 10 vid_in[4] in lv vsb3v cpu vid input pin. special level input vih ? 0.9, vil ? 0.6 vid_in[3] cpu vid input pin. special level input vih ? 0.9, vil ? 0.6 11 svc_in in lv vsb3v svc (serial vid clock)-open drain output of the processor. connect to this pin to the processor. vid_in[2] cpu vid input pin. special level input vih ? 0.9, vil ? 0.6 12 svd_in i/od 12lv vsb3v svd (serial vid data)-bidirectional signal that is an input and open drain output for both master and slave devices. connect to this pin to the processor. 13 vid_in[1] in lv vsb3v cpu vid input pin. special level input vih ? 0.9, vil ? 0.6 14 vid_in[0] in lv vsb3v cpu vid input pin. special level input vih ? 0.9, vil ? 0.6 15 vid_out[0] od 12 vsb3v cpu vid output pin. special level input vih ? 0.9, vil ? 0.6 16 vid_out[1] od 12 vsb3v cpu vid output pin. special level input vih ? 0.9, vil ? 0.6 vid_out[2] cpu vid output pin. special level input vih ? 0.9, vil ? 0.6 17 svc_out od 12 vsb3v svc(serial vid clock)-open dr ain output of the F75125. connect to this pin to the voltage regulator. vid_out[3] cpu vid output pin. special level input vih ? 0.9, vil ? 0.6 18 svd_out i/od 12 vsb3v svd (serial vid data)-bidirectional signal that is an input and open drain output for both master and slave devices. connect to this pin to the voltage regulator. 19 vid_out[4] od 12 vsb3v cpu vid output pin. special level input vih ? 0.9, vil ? 0.6 4.4. power good pin pin no. pin name type pwr description 21 vr_dis_in in lv vsb3v vr disable signal input. the source is nor s3# and vldt. vr_dis_in < 0.6v, vr_en goes high. vr_dis_in > 0.9v, vr_ren goes low.
finte k feature integration technology inc. v0.16p 10 F75125 22 cpu_pg_in in st vsb3v cpu power good signal input, usually from the south bridge 4.5. voltage sense input/voltage sense output pin pin no. pin name type pwr description 1 vsi_1 ain vsb3v voltage sensor channel 1 input for vcore or v nb change use. 2 vso_1 aout vsb3v voltage sensor channel 1 output for vcore or v nb change use. 27 vso_2 aout vsb3v voltage sensor channel 2 output for vcore or v nb change use. 28 vso_1 ain vsb3v voltage sensor channel 2 input for vcore or v nb change use. 4.6. i2c interface pin pin no. pin name type pwr description 24 scl in st vsb3v i2c interface, serial clock input pin. 25 sda i/od 12st vsb3v i2c interface, serial data pin. 4.7. miscellaneous pin pin no. pin name type pwr description 7 vfixen in lv vsb3v hardware jumper input that selects normal operation mode or vfix mode. when vfixen inserts, the voltage regulator will enter vfix mode. 9 core_type in lv vsb3v processor core_type input. in amd npt family 0fh, core_type is floating in amd npt family 10h, core_type is tied to vss at package. 20 vr_en od 12 vsb3v active-high signal enables the vid vr 23 slotocc# in st vsb3v cpu slotocc# input.
finte k feature integration technology inc. v0.16p 11 F75125 5 electrical characteristic 5.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under abso lute maximum ratings may adversely affect the life and reliability of the device 5.2 dc characteristics (ta = 0 c to 70 c, vcc = 3.3v 10%, vss = 0v) parameter sym. min. typ. max. unit conditions od 12 - open-drain output with12 ma sink capability. output low current iol +12 ma vol = 0.4v input high leakage ilih +1 a vin = vcc input low leakage ilil -1 a vin = 0v i/od 12st -ttl level bi-directional pin with schmitt tri gger, output pin with 12ma sink capability. input low threshold voltage vt- 0.8 v vcc = 3.3 v input high threshold voltage vt+ 2.0 v vcc = 3.3 v output low current iol -12 -9 ma vol = 0.4 v input high leakage ilih +1 a vin = vcc input low leakage ilil -1 a vin = 0v i/od 12lv -low voltage bi-directional pin, open drain output pin with 12ma sink capability. input low threshold voltage vt- 0.6 v vcc = 3.3 v input high threshold voltage vt+ 0.9 v vcc = 3.3 v output low current iol -12 -9 ma vol = 0.4 v output high current ioh +9 +12 ma voh = 2.4v input high leakage ilih +1 a vin = 1.2v input low leakage ilil -1 a vin = 0v in lv - low level input pin input low voltage vil 0.6 v input high voltage vih 0.9 v input high leakage ilih +1 a vin = 1.2v
finte k feature integration technology inc. v0.16p 12 F75125 input low leakage ilil -1 a vin = 0 v o 12 - output pin with 12ma source-sink capability. output low current iol -12 -9 ma vol = 0.4 v output high current ioh +9 +12 ma voh = 2.4v input high leakage ilih +1 a vin = vcc input low leakage ilil -1 a vin = 0v 5.3 ac characteristics valid data scl sda in sda out t hd;sta t scl t hd;dat t su;sto t su;dat serial bus timing diagram t r t r t del;dat figure2. smbus timing diagram serial bus timing parameter symbol min max unit scl clock period t - scl 3 us start condition hold time t hd;sda 50 ns stop condition setup-up time t su;sto 50 ns data to scl setup time t su;dat 50 ns data to scl hold time t hd;dat 5 ns data out to scl delay time t del:data 200 ns scl and sda rise time t r 200 ns scl and sda fall time t f 200 ns
finte k feature integration technology inc. v0.16p 13 F75125 valid data svc svd in svd out t hd;sta t svc t hd;dat t su;sto t su;dat serial bus timing diagram t r t r t del;dat figure3. serial vid timing diagram serial vid interface timing parameter symbol min. max. unit scl clock period t - scl 2 us start condition hold time t hd;sda 50 ns stop condition setup-up time t su;sto 50 ns data to scl setup time t su;dat 50 ns data to scl hold time t hd;dat 5 ns data out to scl delay time t del:data 200 ns scl and sda rise time t r 200 ns scl and sda fall time t f 200 ns
finte k feature integration technology inc. v0.16p 14 F75125 6 functional description 6.1 linear con parallel vid interface the F75125 supports 6-bit parallel vid interf ace (pvi). the 6-bit parallel vid codes and the corresponding reference voltage are shown in table 1. it is recommended to connect vid[0:4] output of am2 or am2+ and vid[0:4] input of voltage regulator (vr) controller with F75125 due to the pin-out constraint and tied vid[5] input of the vr controller to vss. the connection can correspond to reference voltage from 1.55v to 0.775v. the corre sponding reference voltage is from 0.800v to 1.550v in concerns of the translation between serial vid interface (svi) and pvi. the vid output is adjustable according to the parallel vid table on-the-fly or by vsi/vso function through i2c interface. table 1. 6-bit parallel vid codes vid5 vid4 vid3 vid2 vid1 vid0 vref 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000 0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000 0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500
finte k feature integration technology inc. v0.16p 15 F75125 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500 1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625 1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625
finte k feature integration technology inc. v0.16p 16 F75125 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875 1 1 1 1 1 1 0.3750 6.2 serial vid interface the serial vid interface (svi) circuitry allows am2+ to direct ly drive the core voltage and northbridge voltage reference level with the svi vr controller. the svc and svd states are de coded with direction from the pwrok and vfixen inputs as described in the following sections. the F75125 is built-in svi cli ent to translate svi to pvi. it can help the pvi vr controll er keep supporting am2+ in svi mode to reduce extra cost to adapt the hybrid vr controller (svi+ pvi) or the svi vr controller. the vid codes output translated form svi is also adjustable from 0.800v to 1.550v according to the vid table on-the-fly by i2c interface. if the output is beyo nd the vid table, it can be tun ed by vsi/vso function, too.
finte k feature integration technology inc. v0.16p 17 F75125 table 2. serial vid codes svid[6:0] vref svid[6:0] vref svid[6:0] vref svid[6:0] vref 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500 * 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375 * 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250 * 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125 * 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.3000 * 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.2875 * 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.2750 * 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0111 0.2625 * 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.2500 * 000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.2375 * 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.2250 * 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.2125 * 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.2000 * 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.1875 * 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.1750 * 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.1625 * 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.1500 * 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.1375 * 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.1250 * 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.1125 * 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.1000 * 001_0101 1.2875 011_0101 0.8875 101_0101 0.4875 * 111_0101 0.0875 * 001_0110 1.2750 011_0110 0.8750 101_0110 0.4750 * 111_0110 0.0750 * 001_0111 1.2625 011_0111 0.8625 101_0111 0.4625 * 111_0111 0.0625 * 001_1000 1.2500 011_1000 0.8500 101_1000 0.4500 * 111_1000 0.0500 * 001_1001 1.2375 011_1001 0.8375 101_1001 0.4375 * 111_1001 0.0375 * 001_1010 1.2250 011_1010 0.8250 101_1010 0.4250 * 111_1010 0.0250 * 001_1011 1.2125 011_1011 0.8125 101_1011 0.4125 * 111_1011 0.0125 * 001_1100 1.2000 011_1100 0.8000 101_1100 0.4000 * 111_1100 off 001_1101 1.1875 011_1101 0.7875 101_1101 0.3875 * 111_1101 off 001_1110 1.1750 011_1110 0.7750 101_1110 0.3750 * 111_1110 off 001_1111 1.1625 011_1111 0.7625 101_1111 0.3625 * 111_1111 off note: * indicates a vid not required for amd family 10h processors (am2+).
finte k feature integration technology inc. v0.16p 18 F75125 6.3 2-bit boot code and vfixen mode vfixen is an input signal used to indicate the vr contro ller in the vfix mode. if anytime vfixen is asserted, the vr controller must enter vfix mode. when in vfix mode, all of the vr controller?s output voltage will be governed by the information shown in table 4. however, the pvi vr controller doesn?t integrate the vfixen input pin, the F75125 can translate the vfixen, svc, and svd to pvi codes to indicate the pvi vr controller in the vfix mode. pre-pwrok metal vid, 2-bit boot code typical motherboard start-up occurs with the vfixen input low. the F75125 decodes the svc and svd inputs to determine the pre-pwrok metal vid setting. after pwrok is asserted, the processor initializes the svi, and the serial vid codes are used. table 3. pre-pwrok metal vid codes svc svd output voltage (v) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 vfix mode in vfix mode, the svc, svd, and vfixen inputs are fixed ex ternal to controller through jumpers to either gnd or vddio. if vfixen is high, the F75125 decodes the svc and svd states per table 4 regardless of the state of pwrok. once enable, the vr controller and the exter nal single phase pwm begin to soft-start both vdd and vddnb planes. table 4. vfix mode vid codes svc svd output voltage (v) 0 0 1.4 0 1 1.2 1 0 1.0 1 1 0.8 6.4 north bridge reference voltage and enable the pvi vr controller which is designed for am2 or prio r processor doesn?t integrate the second precision voltage regulation system for the north bridge portion of am2+. in order to forward compatible to am2+, the F75125
finte k feature integration technology inc. v0.16p 19 F75125 provides the north bridge reference voltage output, nb_v ref, and north bridge voltage enable signal, nb_en#, to the external single phase pwm which provides the no rth bridge voltage. the F75125 successfully decodes the information north bridge voltage determines as the proc essor in the svi mode, and then the nb_vref is in the soft-start process. the nb_en# will be asserted high to low when the nb_vref is over 0.3v. both nb_vref and nb_en# will be disabled as the processor in pvi mode. t he nb_vref output is adjustabl e from 0.3v to 2.04v by i2c interface. per step is 12.5mv. another application of the F75125 is to support svi output. pull high nb_en# to 3,3vsb before pok, and then the F75125 will switch the output mode to svi output. in svi output mode, the F75125 will translate pvid to the corresponding svid and issue vdd_nb an off command (111_1 111 in svid table) to disable vdd_nb output of voltage regulator as am2 implemented*1. note: *1 the chosen voltage regulator must support svid off command, or vdd_nb keeps outputting as amd implemented. 6.5 power saving mode the power saving mode is supported in svi mode. serial vi d codes are transmitted as part of an 8-bit data phase over the svi. the bits are allocated as defined in table 5. table 5. serial vid 8-bit data field encoding bits description 7 psi_l: =0, means the processor is at an optimal load for the regulator(s) to enter power saving mode =1, means the processor is not at an optimal load for the regulator(s) to enter power saving mode 6:0 svid[6:0] as defined in table 2. in am2+ platform, the truth table of psi# and svid_in[7] is defined in table 6. table 6. svid_in[7], svid_out[7] relationship svid_in[7]*1 svid_out[7]*2 remark 0 0 am2+ is at a light load conditi on for the regulator(s) to enter power saving mode 1 1 am2+ is not at a light load condi tion for the regulator(s) to enter power saving mode
finte k feature integration technology inc. v0.16p 20 F75125 note: *1 svid_in[7] is output by the processor to the F75125 *2 svid_out[7] is output by the f 75125 to the vcore voltage regulator 6.6 core_type the core_type is used to indicate which kind of processo r placed and which kind of vi d codes should be issued by the processor. according to amd?s reference circuit, the vid[1] is recommended tied with core_type. in am2, core_type is floating, and vid[1] is driven to vddio by the pr ocessor. the processor w ill issue the parallel vid codes. in am2+, core_type is tied to vss at the package, and vid[1] is driven low via strap to ground. the processor will issue the serial vid co des. core_type is also connected to the F75125 to indicate which kind of vid codes will be decoded. 6.7 voltage sense input/ voltage sense output the voltage sense input (vsi) and voltage sense output (vso) are designed for another option of over voltage, especially beyond the vid table, 1.55v. ev ery step of over voltage is 1.5% more of the current voltage. total tuning steps are 32 steps, so the maximum tuning range up is to 2.325v. figure 4 vsi/vso function illustration vsi vso vref _ + f72815 F75125 vsi vi _ + multi-phase pwm F75125 vref vout vout vout = vref * (1 + n * 0.01613) n = 0,1,2??31 vso
finte k feature integration technology inc. v0.16p 21 F75125 6.8 i2c interface the F75125 can be connected to a compatible 2-wire se rial system management bus (smbus) as a slave device under the control of the master device, using two device terminals scl and sda. the controller can provide a clock signal to the device scl pin and read/write data from /to the device through the device sda pin. the address default is 0x5c(0101_1100) and the oper ation of device to the bus is described with details in the following sections. (a) smbus write to internal address register followed by the data byte 0 start by master 01011 11 d7 d6 d5 d4 d3 d2 d1 d0 ack by 125 r/w ack by 125 sclk sda d7 d6 d5 d4 d3 d2 d1 d0 stop by master scl sda (continued) 780 78 0 78 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte figure 5. serial bus write to internal address register followed by the data byte (b) serial bus write to internal address register only 0 start by master 01011 11 d7 d6 d5 d4 d3 d2 d1 d0 ack by 125 r/w ack by 125 scl sda 780 78 0 frame 2 internal index register byte frame 1 serial bus address byte figure 6. serial bus write to internal address register only stop by master (c) serial bus read from a register with the in ternal address register prefer to desired location 0 start by master 01011 11 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by 125 scl sda 780 78 1 frame 2 internal index register byte frame 1 serial bus address byte figure 7. serial bus read from internal address register stop by master
finte k feature integration technology inc. v0.16p 22 F75125 7 register description (i2c address = 0x5c) 7.1 vddnb voltage value register ? index 00h bit name r/w default description 7-0 vddnb r/w xx vddnb value, the default value is latch from svc and svd vfixen=1 svc,svd=0, the vddnb default is 0x0c (1.4v) svc,svd=1, the vddnb default is 0x1c (1.2v) svc,svd=2, the vddnb default is 0x2c (1.0v) svc,svd=3, the vddnb default is 0x3c (0.8v) vfixen=0 svc,svd=0, the vddnb default is 0x24 (1.1v) svc,svd=1, the vddnb default is 0x2c (1.0v) svc,svd=2, the vddnb default is 0x34 (0.9v) svc,svd=3, the vddnb default is 0x3c (0.8v) manual disable(cr0a bit0 ?0?) this register can program by svi interface by id 8?b110x_xx10. manual enable(cr0a bit0 ?1?) programming by i2c interface and protect by key cr03 .
finte k feature integration technology inc. v0.16p 23 F75125 7.2 vdd0 voltage value register ? index 01h bit name r/w default description 7-0 vdd0 r/w xx vdd0 value, the default value is latch from svc and svd vfixen=1 svc,svd=0, the vdd0 default is 0x0c (1.4v) svc,svd=1, the vdd0 default is 0x1c (1.2v) svc,svd=2, the vdd0 default is 0x2c (1.0v) svc,svd=3, the vdd0 default is 0x3c (0.8v) vfixen=0 svc,svd=0, the vdd0 default is 0x24 (1.1v) svc,svd=1, the vdd0 default is 0x2c (1.0v) svc,svd=2, the vdd0 default is 0x34 (0.9v) svc,svd=3, the vdd0 default is 0x3c (0.8v) manual disable(cr0a bit0 ?0?) this register can program by svi interface by id 8?b110x_x1x0 manual enable(cr0a bit0 ?1?) programming by i2c interface and protect by key cr03. 7.3 vdd1 voltage value register ? index 02h bit name r/w default description 7-0 vdd1 r/w xx vdd1 value, the default value is latch from svc and svd vfixen=1 svc,svd=0, the vdd0 default is 0x0c (1.4v) svc,svd=1, the vdd0 default is 0x1c (1.2v) svc,svd=2, the vdd0 default is 0x2c (1.0v) svc,svd=3, the vdd0 default is 0x3c (0.8v) vfixen=0 svc,svd=0, the vdd0 default is 0x24 (1.1v) svc,svd=1, the vdd0 default is 0x2c (1.0v) svc,svd=2, the vdd0 default is 0x34 (0.9v) svc,svd=3, the vdd0 default is 0x3c (0.8v) manual disable(cr0a bit0 ?0?) this register can program by svi interface by id 8?b110x_1xx0 manual enable(cr0a bit0 ?1?) programming by i2c interface and protect by key cr03.
finte k feature integration technology inc. v0.16p 24 F75125 7.4 vid key protect register ? index 03h bit name r/w default description 7-0 vid_key r/w 0 enter key by 0x32 ? 0x5d ? 0x42 ? 0xac when into key the reading value in this register will be 0xff. exit key by 0x35 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled). 7.5 vddnb voltage offset value register ? index 04h bit name r/w default description 7-0 nb_offset r/w 0 0x00: vddnb voltage = vddnb value(cr00) 0x01: vddnb voltage = vddnb value(cr00) + 1 voltage step(12.5mv) 0x7f: vddnb voltage = vddnb value(cr00) + 127 voltage step(12.5mv) but maximum value is 1.55v 0xff: vddnb voltage = vddnb value(cr00) - 1 voltage step(12.5mv) 0x80: vddnb voltage = vddnb value(cr00) - 128 voltage step(12.5mv) but minimum value is 0.0125v this register is write protect by enter key cr03 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled). 7.6 vdd0 voltage offset value register ? index 05h bit name r/w default description 7-0 vdd0_offset r/w 0 0x00:vdd0 voltage = vdd0 value(cr01) 0x01:vdd0 voltage = vdd0 value(cr01) + 1 step(12.5mv) 0x7f:vdd0 voltage = vdd0 value(cr01) + 127 step(12.5mv) but maximum value is 1.55v 0xff:vdd0 voltage = vdd0 value(cr01) - 1 step(12.5mv) 0x80:vdd0 voltage = vdd0 value(cr01) - 128 step(12.5mv) but minimum value is 0.0125 ( in serial to parallel mode minimum value is 0.7875v) this register is write protect by enter key cr03 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled).
finte k feature integration technology inc. v0.16p 25 F75125 7.7 vdd1 voltage offset value register ? index 06h bit name r/w default description 7-0 vdd1_offset r/w 0 0x00:vdd1 voltage = vdd1 value(cr02) 0x01:vdd1 voltage = vdd1 value(cr02) + 1 step (12.5mv) 0x7f:vdd1 voltage = vdd1 value(cr02) + 127 step (12.5mv) but maximum value is 1.55v 0xff:vdd1 voltage = vdd1 value(cr02) - 1 step(12.5mv) 0x80:vdd1 voltage = vdd1 value(cr02) - 128 step (12.5mv) but minimum value is 0.0125v this register is write protect by enter key cr03 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled). 7.8 vddnb step time register ? index 07h bit name r/w default description 7-4 reserved r 0 3 _ 0 step_time_sel r/w 2 0: direct load expect voltage (cr00+cr04) to nb_vref pin 1: nb_vref change voltage by st ep(8mv), each step is 100us 2: nb_vref change voltage by st ep(8mv), each step is 200us but in power on nb_vref soft start the rise time is 8mv per 100us this register is write protect by enter key cr03 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled). 7.9 vsi/vso 1 over voltage select reading register ? index 08h bit name r/w default description 7-5 reserved r 0 4-0 switch_sel_1 r/w 0 vout = vref *( 1 + (switch_sel_0*0.01613) ) please refer figure 4,p16 this register is write protect by enter key cr03 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled).
finte k feature integration technology inc. v0.16p 26 F75125 7.10 vsi/vso 2 over voltage select reading register ? index 09h bit name r/w default description 7-5 reserved r 0 4-0 switch_sel_2 r/w 0 vout = vref *( 1 + (switch_sel_0*0.01613) ) please refer figure 4,p16 this register is write protect by enter key cr03 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled). 7.11 vdd0, vdd1 and vddnb manual enable register ? index 0ah bit name r/w default description 7-6 reserved r 0 reserved, 5 vdd0_mirror_en r/w 0 in serial vid output mode, if this bit is set to 1, vdd0 will follow vid value of vddnb. 4 nb_mirror_en r/w 0 in serial vid output mode, if this bit is set to 1, vddnb will follow vid value of vdd0. 3-1 reserved r 0 reserved, 0 manual_en r/w 0 00: manual mode is disabled. 01: serial to parallel manual mode is enabled, but parallel to parallel keep in bypass mode. 10: reserved. 11: serial to parallel and parallel to parallel manual mode enabled. when F75125 manual mode enable, user can program cr00 , cr01 and cr02 by i2c interface, and cr00 val ue will direct to control nb_vref voltage (each step is 12.5mv) cr01 value + cr05 offset value will output to vid out. this register is write protect by enter key cr03 it can be reset by watchdog timeout. if cr0 f[0] is set to 1, it can be reset by slotocc# pin, too (default is disabled). 7.12 nb_vref voltage reading register (lsb) ? index 0bh bit name r/w default description 7-0 nb_vid_out r 0 {1?b0,vid_out_nb} * 8mv
finte k feature integration technology inc. v0.16p 27 F75125 7.13 vddnb svi output r eading register (lsb) ? index 0ch bit name r/w default description 7-0 nb _out r 0 svid_out_nb (cr00+cr04) 7.14 vdd0 svi output reading register (lsb) ? index 0dh bit name r/w default description 7-0 vdd0_out r 0 svid_out_vdd0 (cr01+cr05) 7.15 vdd1 svi output reading register (lsb) ? index 0eh bit name r/w default description 7-0 vdd1_out r 0 svid_out_vdd1(cr02+cr06) 7.16 slotocc control enable reading register ? index 0fh bit name r/w default description 7 reserved r 1 reserved 6-1 dummy_reg r/w 0 dummy registers. 0 slotocc_clr_en r/w 0 enable slotocc# pin to clear register 7.17 vdd_nb voltage value register ? index 10h bit name r/w default description 7-0 vddnb r xx this register can read vid value that input from svi interface. this register presents all the svid code including bit 7, psi_l. 7.18 vdd0 voltage value register ? index 11h bit name r/w default description 7-0 vdd0 r xx this register can read vid value that input from pvi/svi interface. in pvi input mode, msb and lsb will be inserted ?0? to complement 8 bit register. for example, pvid code ?111_111? will be read as 0x7e. in svi mode, this register presents all the svi d code including bit 7, psi_l.
finte k feature integration technology inc. v0.16p 28 F75125 7.19 vdd1 voltage value register ? index 12h bit name r/w default description 7-0 vdd1 r xx this register can read vid value that input from svi interface. this register presents all the svid code including bit 7, psi_l. 7.20 vid timeout value select register ? index 13h bit name r/w default description 7 timer_en r/w 0 set to 1 to enable vid watchdog timer.. 6-0 count_value r/w 7?h0 when timer_en is set to 1 and counter value down count to zero, it will generate one reset pulse to clear inte rnal registers and timer_en bit will auto clear to 0. 7.21 chip id1 register ? index 5ah bit name r/w default description 7-0 chip_id1 r 07h chip id1 7.22 chip id2 register ? index 5bh bit name r/w default description 7-6 chip_id2 r 03h chip id2 7.23 version id register ? index 5ch bit name r/w default description 7-0 ver_id r 30h version id 7.24 vendor id1 register ? index 5dh bit name r/w default description 7-0 vendor_id1 r 19h vendor id1 7.25 vendor id2 register ? index 5eh bit name r/w default description 7-0 vendor_id2 r 34h vendor id2
finte k feature integration technology inc. v0.16p 29 F75125 8 ordering information part number package type production flow F75125r 28-ssop (green package) commercial, 0 c to +70 c 9 package dimensions (28-ssop) figure 8. 28 pin ssop package diagram
finte k feature integration technology inc. v0.16p 30 F75125 feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw
finte k feature integration technology inc. v0.16p 31 F75125 please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r
finte k feature integration technology inc. v0.16p 32 F75125 10 application circuit figure 9. F75125r parallel vid output application circuit
finte k feature integration technology inc. v0.16p 33 F75125 figure 10. F75125r serial vid output application circuit

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